并发编程网 - ifeve.com

声明：本文是《Java虚拟机并发编程》的第六章，感谢华章出版社授权并发编程网站发布此文，禁止以任何形式转载此文。

请回忆一下你最近完成那个需要对共享可变变量进行同步的项目。在那个项目中，你肯定无法身心愉悦地享受出色地完成工作所带来的乐趣，而是会陷入无尽的质疑之中并抓狂地挨个确认是否在所有需要的地方都作了适当的同步。在过去所经历过的编程工作中，我已经遇到过好几次这样令人神经衰弱的情况了，而其中绝大部分原因都是由于我们在用Java编程的时候没有遵循正确原则和方法来处理共享可变状态。如果我们在某个该同步的地方忘了进行同步，那些不可预知的、潜在的灾难性的结果就将在不远处等待着我们。但是人无完人，遗忘是我们的天性。所以我们应该充分利用工具来弥补我们自身的不足，同时也可以让工具帮助我们实现我们充满创意的大脑所追求的那些伟大的目标，而不是让错误一次次地打击我们的信心。为了能够得到可控的行为和结果，我们需要再次把目光投向JDK。

在本章中，我们将会通过使用Clojure中十分流行的软件事务内存（STM）模型来学习如何线程安全地处理共享可变性（shared mutability）。在需要的时候，我们可能会在示例项目中混入Clojure的代码。但是我们并非强迫你也要使用Clojure，因为随着Multiverse和Akka这些优秀工具的出现，我们也可以在Java中直接使用STM了。在本章中，我们会先来看看STM在Clojure里是什么样子，然后再学习如何用Java和Scala对事务内存进行编程。这种编程模型非常适用于那些读多写少的程序——它简单易用并能提供可预测的结果。 阅读全文

并发编程网站

1. Thread newsgroup(很多多线程相关的问题)
2. preshing
   
3. Doug Lea workstation （并发编程大师Doug lea的个人网站）
4. Concurrency mail list  (Doug lea搞的邮件列表)
5. oracle dave  (oracle 并发编程小组成员)
6. lycog.com
7. edu papers （很多并发编程相关的论文）
8. oracle concurrency （oracle网站）
9. mechanical-sympathy（需要翻墙，主要分享如何利用硬件的特性来实现高性能编程）
10. Quora concurrency (quora问答网站的并发问题讨论)
11. stackoverflow concurrency(stackoverflow问答网站的并发问题讨论)
12. developerworks concurrency（并发编程专题文章）
13. tumblr concurrency （涵盖多个语言的并发相关文章）
14. JDK concurrent(官方jdk1.6 concurrent包API中文文档)
15. trans-memory （研究内存事务的网站)

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• 并发编程实战
• Erlang/OTP并发编程实战
• Java虚拟机并发编程
• 多处理器编程的艺术
• Windows并发编程指南
• Go语言编程

Doug Lea’s Home Page

如果IT的历史，是以人为主体串接起来的话，那么肯定少不了Doug Lea。这个鼻梁挂着眼镜，留着德王威廉二世的胡子，脸上永远挂着谦逊腼腆笑容，服务于纽约州立大学Oswego分校计算机科学系的老大爷。

说他是这个世界上对Java影响力最大的个人，一点也不为过。因为两次Java历史上的大变革，他都间接或直接的扮演了举足轻重的角色。一次是由JDK 1.1到JDK 1.2，JDK1.2很重要的一项新创举就是Collections，其Collections的概念可以说承袭自Doug Lea于1995年发布的第一个被广泛应用的collections；一次是2004年所推出的Tiger。Tiger广纳了15项JSRs(Java Specification Requests)的语法及标准，其中一项便是JSR-166。JSR-166是来自于Doug编写的util.concurrent包。(摘自百度) 阅读全文

原文地址：http://mechanical-sympathy.blogspot.com/2013/01/further-adventures-with-cas.html

In a previous article I reported what appeared to be a performance issue with CAS/LOCK instructions on the Sandy Bridge microarchitecture compared to the previous Nehalem microarchitecture.  Since then I’ve worked with the good people of Intel to understand what was going on and I’m now pleased to be able to shine some light on the previous results.

I observed a small drop in throughput with the uncontended single-thread case, and an order-of-magnitude decrease in throughput once multiple threads contend when performing updates.  This testing spawned out of observations testing Java Queue implementations and the Disruptor for the multi-producer case.  I was initially puzzled by these findings because almost every other performance test I applied to Sandy Bridge indicated a major step forward for this microarchitecture. 阅读全文

原文地址：http://mechanical-sympathy.blogspot.com/2011/08/inter-thread-latency.html （移到墙内）

Message rates between threads are fundamentally determined by the latency of memory exchange between CPU cores.   The minimum unit of transfer will be a cache line exchanged via shared caches or socket interconnects.  In a previous article I explained Memory Barriers and why they are important to concurrent programming between threads.  These are the instructions that cause a CPU to make memory visible to other cores in an ordered and timely manner. 阅读全文

原文链接：http://mechanical-sympathy.blogspot.com/2011/07/write-combining.html（有墙移动到墙内）

Modern CPUs employ lots of techniques to counteract the latency cost of going to main memory. These days CPUs can process hundreds of instructions in the time it takes to read or write data to the DRAM memory banks.

The major tool used to hide this latency is multiple layers of SRAM cache. In addition, SMP systems employ message passing protocols to achieve coherence between caches. Unfortunately CPUs are now so fast that even these caches cannot keep up at times. So to further hide this latency a number of less well known buffers are used.

This article explores “write combining store buffers” and how we can write code that uses them effectively.

CPU caches are effectively unchained hash maps where each bucket is typically 64-bytes. This is known as a “cache line”. The cache line is the effective unit of memory transfer. For example, an address A in main memory would hash to map to a given cache line C.

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Mechanical Sympathy（需要翻墙才能访问）是Martin Thompson的博客，这个博客主要讲的是底层硬件是如何运作的，以及如何编程能够与地层硬件良好的协作。英文名称的为未翻译的文章，有兴趣的同学可以领取翻译。

1. CPU缓存刷新的误解
2. 伪共享
3. Java 7与伪共享的新仇旧恨
4. 内存访问模型的重要性
5. Memory Barriers/Fences
6. 合并写
7. 内存屏障

本实践是原阿里巴巴ITU内贸团队打造出的一系列适合团队不断精进的敏捷实践。阿里内贸团队是一支自组织，一体化和全功能的敏捷团队。自组织体现在团队中的每个成员都会得到充分的尊重和自由，每个成员都可以主导某个实践（如项目回顾会议）和改进（如推动团队成员一起提高单元测试覆盖率）。一体化体现在团队合作上。全功能体现在团队成员既可以研发，也可以做前端和测试，从而打破角色边界提高总体产出。我们在进行一次敏捷实践时会经历五个步骤，分别是计划，编码，测试，发布和回顾。注：本图由同事金建法所画。

1. 打造合作型团队
2. 自组织管理
3. 敏捷设计
4. 结对编程
5. 迭代计划
6. 开发自测
7. Code Review
8. 敏捷回顾
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本文是作者原创，原文发表于《程序员》杂志2013年3月刊

实现团队的自组织管理，非常有助于团队形成合力，极大地提升团队整体的工作效率。本文结合原阿里ITU内贸团队的敏捷实践经历，阐释了何为自组织管理、为什么进行自组织管理、如何进行自组织管理等内容，同时给出了团队实施自组织管理的效果。

原文地址：http://mechanical-sympathy.blogspot.com/2012/08/memory-access-patterns-are-important.html（因墙转载）

In high-performance computing it is often said that the cost of a cache-miss is the largest performance penalty for an algorithm.  For many years the increase in speed of our processors has greatly outstripped latency gains to main-memory.  Bandwidth to main-memory has greatly increased via wider, and multi-channel, buses however the latency has not significantly reduced.  To hide this latency our processors employ evermore complex cache sub-systems that have many layers.

The 1994 paper “Hitting the memory wall: implications of the obvious” describes the problem and goes on to argue that caches do not ultimately help because of compulsory cache-misses.  I aim to show that by using access patterns which display consideration for the cache hierarchy, this conclusion is not inevitable.
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原文地址：http://mechanical-sympathy.blogspot.com/2011/07/memory-barriersfences.html（因墙转载)

In this article I’ll discuss the most fundamental technique in concurrent programming known as memory barriers, or fences, that make the memory state within a processor visible to other processors.

CPUs have employed many techniques to try and accommodate the fact that CPU execution unit performance has greatly outpaced main memory performance.  In my “Write Combining” article I touched on just one of these techniques.  The most common technique employed by CPUs to hide memory latency is to pipeline instructions and then spend significant effort, and resource, on trying to re-order these pipelines to minimise stalls related to cache misses.

When a program is executed it does not matter if its instructions are re-ordered provided the same end result is achieved.  For example, within a loop it does not matter when the loop counter is updated if no operation within the loop uses it.  The compiler and CPU are free to re-order the instructions to best utilise the CPU provided it is updated by the time the next iteration is about to commence.  Also over the execution of a loop this variable may be stored in a register and never pushed out to cache or main memory, thus it is never visible to another CPU. 阅读全文

本文列出了在工作中会用到的并发编程的实战问题，大家可以一起交流下，在回复中给出答案。

并发容器和框架

1. 如何让一段程序并发的执行，并最终汇总结果？
2. 如何合理的配置java线程池？如CPU密集型的任务，基本线程池应该配置多大？IO密集型的任务，基本线程池应该配置多大？用有界队列好还是无界队列好？任务非常多的时候，使用什么阻塞队列能获取最好的吞吐量？
3. 如何使用阻塞队列实现一个生产者和消费者模型？请写代码。
4. 多读少写的场景应该使用哪个并发容器，为什么使用它？比如你做了一个搜索引擎，搜索引擎每次搜索前需要判断搜索关键词是否在黑名单里，黑名单每天更新一次。 阅读全文

本文是作者原创, 原文发表于程序员2013年2月刊 http://www.programmer.com.cn/15217/  转载请注明出处

本文中，来自阿里内贸团队的工程师分享了所在团队打造合作型“精英”小团队的敏捷实践方法，同时讲述了实践的效果，旨在给大家一些启发，以供参考和借鉴。

原文：http://mechanical-sympathy.blogspot.hk/2011/08/false-sharing-java-7.html （因为被墙移动到墙内）

In my previous post on False Sharing I suggested it can be avoided by padding the cache line with unused longfields.  It seems Java 7 got clever and eliminated or re-ordered the unused fields, thus re-introducing false sharing.  I’ve experimented with a number of techniques on different platforms and found the following code to be the most reliable.

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