原文地址译者：郭蕾 校对：丁一
本文是Java HotSpot VM and just-in-time(JIT) compilation系列的第一篇。
Java HotSpot虚拟机是Oracle收购Sun时获得的，JVM和开源的OpenJDK都是以此虚拟机为基础发展的。如同其它虚拟机，HotSpot虚拟机为字节码提供了一个运行时环境。实际上，它主要会做这三件事情：
最后两点都是各自领域的大话题，所以这篇文章中只关注代码执行。
原文地址：http://mechanical-sympathy.blogspot.com/2011/08/inter-thread-latency.html （移到墙内）
Message rates between threads are fundamentally determined by the latency of memory exchange between CPU cores. The minimum unit of transfer will be a cache line exchanged via shared caches or socket interconnects. In a previous article I explained Memory Barriers and why they are important to concurrent programming between threads. These are the instructions that cause a CPU to make memory visible to other cores in an ordered and timely manner. 阅读全文
原文链接：http://mechanical-sympathy.blogspot.com/2011/07/write-combining.html（有墙移动到墙内）
Modern CPUs employ lots of techniques to counteract the latency cost of going to main memory. These days CPUs can process hundreds of instructions in the time it takes to read or write data to the DRAM memory banks.
The major tool used to hide this latency is multiple layers of SRAM cache. In addition, SMP systems employ message passing protocols to achieve coherence between caches. Unfortunately CPUs are now so fast that even these caches cannot keep up at times. So to further hide this latency a number of less well known buffers are used.
This article explores “write combining store buffers” and how we can write code that uses them effectively.
CPU caches are effectively unchained hash maps where each bucket is typically 64-bytes. This is known as a “cache line”. The cache line is the effective unit of memory transfer. For example, an address A in main memory would hash to map to a given cache line C.
本文介绍了Java原生的多线程技术（1.2），通过详细介绍wait和notify相关的机制、基础的多线程技术以及基于这些技术的等待超时、线程间的通信技术和线程池高阶技术，最后通过一个基于线程池的简单文本web服务器—MollyServer，来阐明多线程带来好处。通过介绍这些技术，展示了在没有使用Java并发包的时代（1.5-）是如何完成Java的多线程编程，为理解Java5提供了良好帮助。
原文地址：http://mechanical-sympathy.blogspot.com/2011/07/memory-barriersfences.html（因墙转载)
In this article I’ll discuss the most fundamental technique in concurrent programming known as memory barriers, or fences, that make the memory state within a processor visible to other processors.
CPUs have employed many techniques to try and accommodate the fact that CPU execution unit performance has greatly outpaced main memory performance. In my “Write Combining” article I touched on just one of these techniques. The most common technique employed by CPUs to hide memory latency is to pipeline instructions and then spend significant effort, and resource, on trying to re-order these pipelines to minimise stalls related to cache misses.
When a program is executed it does not matter if its instructions are re-ordered provided the same end result is achieved. For example, within a loop it does not matter when the loop counter is updated if no operation within the loop uses it. The compiler and CPU are free to re-order the instructions to best utilise the CPU provided it is updated by the time the next iteration is about to commence. Also over the execution of a loop this variable may be stored in a register and never pushed out to cache or main memory, thus it is never visible to another CPU. 阅读全文
原文：http://mechanical-sympathy.blogspot.hk/2011/08/false-sharing-java-7.html （因为被墙移动到墙内）
In my previous post on False Sharing I suggested it can be avoided by padding the cache line with unused longfields. It seems Java 7 got clever and eliminated or re-ordered the unused fields, thus re-introducing false sharing. I’ve experimented with a number of techniques on different platforms and found the following code to be the most reliable.
原文地址：http://mechanical-sympathy.blogspot.com/2013/02/cpu-cache-flushing-fallacy.html （因有墙移动到墙内）
Even from highly experienced technologists I often hear talk about how certain operations cause a CPU cache to “flush”. This seems to be illustrating a very common fallacy about how CPU caches work, and how the cache sub-system interacts with the execution cores. In this article I will attempt to explain the function CPU caches fulfil, and how the cores, which execute our programs of instructions, interact with them. For a concrete example I will dive into one of the latest Intel x86 server CPUs. Other CPUs use similar techniques to achieve the same ends. 阅读全文
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